Power management IPs

nSilition offers energy-efficient power management intellectual property (IP) in order to reach all of your power management needs with your innovative technology.
nSilition’s power management IPs are used to help ASIC/SoC developers achieve best-in-class performance in areas such as noise suppression and efficiency. We want your electronics smaller, smarter and stronger: we lower your costs and we reduce the size.
Our power management IPs include:

  • bandgap-based references,
  • voltage and current reference generators,
  • low drop-out (LDO) regulators,
  • and DC-DC converters (inductor-based, capacitor-based or hybrid).

They are used in various revolutionizing markets such as automotive, space and consumer applications.

Technology RadTol Statussort ascending Product brief
LVDS transmitter cell TSMC 65 GP No Silicon proven PDF icon nSIO_TS65GP_2V5_1V0_TX_PB.pdf
10b 64MSps power-efficient ΔΣ ADC ST 130 M No Silicon proven PDF icon nSAD_ST130M_1V2_AD10b64M_PB.pdf
10b 100MSps high-speed pipeline ADC UMC 180 MM No Silicon proven PDF icon nSAD_UM180M_1V8_AD10b100M_PB.pdf
Radiation-tolerant bandgap reference voltage XFAB XH018 Yes Silicon proven PDF icon nSBG_XF180_1V8_RTBG_PB.pdf
10b 100kSps ultra-low power SAR ADC ST CMOS 65 No Silicon proven PDF icon nSAD_ST65LP_1V2_AD10b100k_PB.pdf
Radiation-tolerant bandgap-based reference voltage generator XFAB XH018 Yes Silicon proven PDF icon nSBG_XF180_1V8_RTVREF_PB.pdf
Bandgap-based reference voltage generator XFAB XH018 No Silicon proven PDF icon nSBG_XF180_1V8_VREF_PB.pdf
LVDS bidirectional transceiver IO cell TSMC 65 LP No Silicon proven PDF icon nSIO_TS65LP_2V5_1V2_BIDIR_PB.pdf
IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO TSMC 65 LP No Silicon proven PDF icon nSIO_TS65LP_2V5_1V2_COMBO_PB.pdf
LVDS IO cells library TSMC 65 LP No Silicon proven PDF icon nSIO_TS65LP_2V5_1V2_LIB_PB.pdf
LVDS receiver cell TSMC 65 LP No Silicon proven PDF icon nSIO_TS65LP_2V5_1V2_RX_PB.pdf
LVDS transmitter cell TSMC 65 LP No Silicon proven PDF icon nSIO_TS65LP_2V5_1V2_TX_PB.pdf
62.5MHz - 2GHz integer-N PLL Silt 130 No Silicon proven PDF icon nSOSC_SI130G_1V2_PLL2G_PB.pdf
LVDS bidirectional transceiver IO cell TSMC 40 G No Silicon proven PDF icon nSIO_TS40G_2V5_0V9_BIDIR_PB.pdf
IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO TSMC 40 G No Silicon proven PDF icon nSIO_TS40G_2V5_0V9_COMBO_PB.pdf
LVDS IO cells library TSMC 40 G No Silicon proven PDF icon nSIO_TS40G_2V5_0V9_LIB_PB.pdf
LVDS receiver cell TSMC 40 G No Silicon proven PDF icon nSIO_TS40G_2V5_0V9_RX_PB.pdf
LVDS transmitter cell TSMC 40 G No Silicon proven PDF icon nSIO_TS40G_2V5_0V9_TX_PB.pdf
LVDS bidirectional transceiver IO cell TSMC 40 LP No Silicon proven PDF icon nSIO_TS40LP_2V5_1V1_BIDIR_PB.pdf
LVDS bidirectional transceiver IO cell TSMC 65 GP No Silicon proven PDF icon nSIO_TS65GP_2V5_1V0_BIDIR_PB.pdf
IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO TSMC 40 LP No Silicon proven PDF icon nSIO_TS40LP_2V5_1V1_COMBO_PB.pdf
IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO TSMC 65 GP No Silicon proven PDF icon nSIO_TS65GP_2V5_1V0_COMBO_PB.pdf
LVDS IO cells library TSMC 40 LP No Silicon proven PDF icon nSIO_TS40LP_2V5_1V1_LIB_PB.pdf
LVDS IO cells library TSMC 65 GP No Silicon proven PDF icon nSIO_TS65GP_2V5_1V0_LIB_PB.pdf
LVDS receiver cell TSMC 40 LP No Silicon proven PDF icon nSIO_TS40LP_2V5_1V1_RX_PB.pdf
LVDS receiver cell TSMC 65 GP No Silicon proven PDF icon nSIO_TS65GP_2V5_1V0_RX_PB.pdf
LVDS transmitter cell TSMC 40 LP No Silicon proven PDF icon nSIO_TS40LP_2V5_1V1_TX_PB.pdf
12b 200MSps dual high-speed pipeline ADC TSMC 90 G No Pre-silicon PDF icon nSAD_TS90G_1V2_AD2x12b200M_PB.pdf
14b 150MSps high-precision pipeline ADC TSMC 130 M No Pre-silicon PDF icon nSAD_TS130M_3V3_1V2_AD14b150M_PB.pdf